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Verilog HDL Synthesis : A Practical Primer
Author: Bhasker, J.

Cover: Soft cover
Pages: 215
List Price: $49.95
Published by Star Galaxy
Date Published: 10/1998
ISBN: 0965039153


The topic of Verilog HDL synthesis has been in existence since 1988. However good textbooks on the topic have not covered basic concepts until now. This practical primer on Verilog HDL synthesis provides a comprehensive and practical description for this new technology. It takes the mystery out of HDL synthesis, by providing an easy to understand Verilog language semantic with respect to synthesis tedhnology. Bhasker is an expert on synthesis: he has worked in synthesis for more than fourteen years. He is currently using his expertise in leading the efforts as the chair of IEEE working group for developing a Verilog RTL synthesis standard (PAR 1364.1) that is based on the OVI1 RTL synthesis subset 1.0 released in April 1998. Bhasker is one of the architects for the OVI standard on RTL synthesis.

"Verilog HDL Synthesis, A Practical Primer" by J. Bhasker provides students and practicing logic designers with immediate access to wellorganized information about Verilog HDL synthesis. It is easy to read and provides a very large number of examples of synthesizable Verilog HDL models. The reader is led systematically from Verilog HDL language constructs, their meaning in synthesis, how synthesis design technology transforms such constructs into gates, and their impact on design verification. The book is rich in Verilog HDL model examples and their gate equivalence. The examples are simple and show the different styles of logic modeling such as combinational logic, sequential logic, and register and latched based design, finite state machines, arithmetic units and others.

The book is not just unique in covering HDL synthesis for beginners, but also goes into advanced topics such as how to get optimized logic from a synthesis model. Resource sharing and allocation is one of the topics covered under model optimization. Another unique topic is design verification. The book goes into the principles of synthesis model writing to ensure predictable and verifiable results. Although the chapter is intended for simulation, the same concepts can be applied for formal verification.

This book is the first comprehensive treatment for Verilog HDL synthesis. Bhasker has taught Verilog HDL and Verilog HDL synthesis at Lucent Technologies for more than three years. The book shows the knowledge that Bhasker has accumulated during his fourteen years on synthesis. Although this book is targeted for beginners, expert users can benefit from the basic principles as well as the advanced modeling topics in synthesis. Definitely, intellectual property (EP) developers should follow the modeling style recommended in this book.

Vassilios C. Gerousis Senior Staff Technologist, Motorola, Phoenix, Arizona Chairman, Technical Coordinating Committee (TCC), Open Verilog International